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ltc4312 1 4312f typical application description pin-selectable, 2-channel, 2-wire multiplexer with bus buffers the ltc ? 4312 is a hot-swappable 2-channel 2-wire bus multiplexer that allows one upstream bus to connect to any combination of downstream busses or channels. an individual enable pin controls each connection. the ltc4312 provides bidirectional buffering, keeping the up- stream bus capacitance isolated from the downstream bus capacitances. the high noise margin allows the ltc4312 to be interoperable with i 2 c devices that drive a high v ol (> 0.4v). the ltc4312 supports level translation between 1.5v, 1.8v, 2.5v, 3.3v and 5v busses. the hot-swappable nature of the ltc4312 allows i/o card insertion into, and removal from, a live backplane without corruption of the data and clock busses. if both data and clock are not simultaneously high at least once in 45ms and discen is high, a fault signal is generated indicating a stuck bus low condition, the input is disconnected from each enabled output channel and up to 16 clocks are generated on the enabled downstream busses. a three state acc pin enables input and output side rise time accelerators of varying strengths and sets the v il,rising voltage. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 6356140, 6650174, 7032051, 7478286. features applications n 1:2 multiplexer/switch for 2-wire bus n bidirectional buffer for sda and scl lines n high noise margin with v il = 0.3?v cc n enable pins connect sda and scl lines n selectable rise time accelerator current and activation voltage n level shift 1.5v, 1.8v, 2.5v, 3.3v and 5v busses n prevents sda and scl corruption during live board insertion and removal from backplane n stuck bus disconnect and recovery n compatible with i 2 c, i 2 c fast mode and smbus n 4kv human body model (hbm) esd ruggedness n 14-lead 4mm 3mm dfn and 16-lead msop packages n telecommunications systems including atca n address expansion n level translator n capacitance buffers/bus extender n live board insertion n pmbus rising edge from asserted low with level translation ltc4312 gnd v cc v cc2 4314 ta01a sclout1 sdaout1 sclout2 sdaout2 sclout1 sdaout1 sclout2 sdaout2 sclin sdain enable1 enable2 acc discen fault sclin sdain enable1 enable2 3.3v 10k fault 10k 10k 0.01f 3.3v 3.3v 10k 10k 5v 10k 10k 0.01f 200ns/div 1v/div 4312 ta01b c sclout1 + c sclout2 = 100pf c sclin = 50pf sclout2 sclout1 sclin 0v 6v 5v 3.3v
ltc4312 2 4312f absolute maximum ratings supply voltage v cc , v cc2 ................................................. C0.3v to 6v input voltages acc , discen, enable1-2 ....................... C0.3v to 6v input/output voltages sdain, sclin, sclout1-2, sdaout1-2, fault ................................. C0.3v to 6v (notes 1, 2) discen acc gnd v cc2 fault enable1 enable2 v cc sclout1 sdaout1 sdain sclin sclout2 sdaout2 top view 15 de14 package 14-lead (4mm = 3mm) plastic dfn 1 2 3 4 5 6 7 14 13 12 11 10 9 8 t jmax = 125c, ja = 43c/w, jc = 5c/w exposed pad (pin #15) pcb connection to gnd is optional 1 2 3 4 5 6 7 8 discen v cc sclout1 sdaout1 sdain sclin sclout2 sdaout2 16 15 14 13 12 11 10 9 acc gnd nc nc v cc2 fault enable1 enable2 top view ms package 16-lead plastic msop t jmax = 150c, ja = 120c/w, jc = 21c/w pin configuration order information lead free finish tape and reel part marking* package description temperature range ltc4312ide#pbf ltc4312ide#trpbf 4312 14-lead (4mm 3mm) dfn C40c to 85c ltc4312ims#pbf ltc4312ims#trpbf 4312 16-lead plastic msop C40c to 85c ltc4312cde#pbf ltc4312cde#trpbf 4312 14-lead (4mm 3mm) dfn 0c to 70c ltc4312cms#pbf ltc4312cms#trpbf 4312 16-lead plastic msop 0c to 70c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ output dc sink currents fault .................................................................50ma operating ambient temperature range ltc4312c ................................................ 0c to 70c ltc4312i.............................................. C40c to 85c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec) msop .............................................................. 300c
ltc4312 3 4312f electrical characteristics symbol parameter conditions min typ max units power supply/start-up v cc input supply range l 2.9 5.5 v v dd, bus 2-wire bus supply voltage l 2.25 5.5 v v cc2 output side accelerator supply range l 2.25 5.5 v i cc input supply current one or both v enable1-2 = v cc = v cc2 = 5.5v (note 3) l 6.0 7.3 9 ma i cc(disabled) input supply current v enable1-2 = 0v; v cc = v cc2 = 5.5v (note 3) l 1.6 2.2 3.5 ma i cc2 v cc2 supply current one or both v enable1-2 = v cc = v cc2 = 5.5v (note 3) l 0.35 0.5 0.6 ma t uvlo uvlo delay l 60 110 200 s v th_uvlo uvlo threshold l 2.3 2.6 v v cc_uvlo(hyst) uvlo threshold hysteresis voltage 200 mv buffers v os1(sat) buffer offset voltage i ol = 4ma, driven v sdain,sclin = 50mv l 130 220 280 mv i ol = 500a, driven v sdain,sclin = 50mv l 15 60 120 mv v os2(sat) buffer offset voltage i ol = 4ma, driven v sdaout, sclout = 50mv l 90 190 260 mv i ol = 500a, driven v sdaout, sclout = 50mv l 15 55 110 mv v os buffer offset voltage i ol = 4ma, driven v sdain,sclin = 200mv l 50 130 195 mv i ol = 500a, driven v sdain,sclin = 200mv l 15 55 110 mv v os2 buffer offset voltage i ol = 4ma, driven v sdaout,sclout = 200mv l 35 95 170 mv i ol = 500a, driven v sdaout,sclout = 200mv l 15 50 100 mv v il,falling buffer input logic low voltage sda, scl pins (notes 4, 5) l 0.3?v min 0.33?v min 0.36?v min v v il,rising buffer input logic low voltage sda, scl pins; acc grounded l 0.5 0.6 0.7 v sda, scl pins; acc open or high (notes 4, 5) l 0.3?v min 0.33?v min 0.36?v min v i leak input leakage current sda, scl pins; v cc , v cc2 = 0v, 5.5v l 10 a c in input capacitance sda, scl pins (note 6) <20 pf rise time accelerators dv/dt (rta) minimum slew rate requirement sda, scl pins; v cc = v cc2 = 5v l 0.1 0.2 0.4 v/s v rta(th) rise time accelerator dc threshold voltage sda, scl pins; v cc = v cc2 = 5v, acc grounded l 0.7 0.8 0.9 v acc open or high, v cc = v cc2 = 5v (note 4) l 0.36?v min 0.4?v min 0.44?v min v v acc buffers off to accelerator on voltage sda, scl pins; v cc = v cc2 = 5v, acc grounded l 100 200 mv acc open, v cc = v cc2 = 5v (note 4) l 0.05?v min 0.07?v min mv i rta rise time accelerator pull-up current sda, scl pins; v cc = v cc2 = 5v, acc grounded (note 7) l 20 35 45 ma acc open, v cc = v cc2 = 5v (note 7) l 1.5 3 4 ma enable/control v discen(th) discen threshold voltage l 0.8 1.4 2 v v discen(hyst) discen hysteresis voltage 20 mv v en(th) enable1-2 threshold voltage l 0.8 1.4 2 v v en(hyst) enable1-2 hysteresis voltage 20 mv t lh_en enable1-2 high to buffer active 0.56 1 s the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = v cc2 = 3.3v unless otherwise noted.
ltc4312 4 4312f electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = v cc2 = 3.3v unless otherwise noted. symbol parameter conditions min typ max units i leak input leakage current discen = enable1-2 = 5.5v l 0.1 10 a i acc (in, hl) acc high, low input current v cc = 5v, v acc = 5v, 0v l 23 40 a i acc (in, z) allowable leakage current in open state v cc = 5v l 5 a i acc (en, z) acc high z input current v cc = 5v l 5 a v acc (l, th) acc input low threshold voltages v cc = 5v l 0.2?v cc 0.3?v cc 0.4?v cc v v acc (h,th) acc input high threshold voltages v cc = 5v l 0.7?v cc 0.8?v cc 0.9?v cc v stuck low timeout circuitry t timeout bus stuck low timer sdaout or sclout < 0.3?v cc l 35 45 55 ms v fault (ol) fault output low voltage i fault = 3ma l 0.4 v i fault (oh) fault leakage current l 0.1 5 a i 2 c interface timing f scl(max) i 2 c frequency max (note 6) l 400 khz t pdhl sda, scl fall delay v cc = 3v to 5.5v, c bus = 50pf, i bus = 1ma (note 6) 60 100 ns t f sda, scl fall times v cc = 3v to 5.5v, c bus = 50pf, i bus = 1ma (note 6) 10 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into pins are positive and all voltages are referenced to gnd unless otherwise indicated. note 3: sdain, sclin pulled low. note 4: v min = minimum of v cc and v cc2 if v cc2 > 2.25v else v min = v cc . note 5: v il is tested for the following (v cc , v cc2 ) combinations: (2.9v, 5.5v), (5.5v, 2.25v), (3.3v, 3.3v) and (5v, 0v). note 6: guaranteed by design and not tested. note 7: measured in a special dc mode with v sda,scl = v rta(th) + 1v. the transient i rta seen during rising edges when acc is low will depend on the bus loading condition and the slew rate of the bus. the ltc4312s internal slew rate control circuitry limits the maximum bus rise rate to 75v/s by controlling the transient i rta .
ltc4312 5 4312f typical performance characteristics rise time accelerator current vs temperature buffer high to low propagation delay vs output capacitance input to output offset voltage vs bus current for different driven input voltage levels output to input offset voltage vs bus current for different driven output voltage levels i cc enabled current vs supply voltage i cc disabled (enable1-2 low) current vs supply voltage multiplexer switch resistance r mux vs temperature t a = 25c, v cc = 3.3v unless otherwise noted. buffer dc i ol vs temperature temperature (c) C50 r mux () 10 5 6 7 8 9 4 50 0 4312 g03 100 25 C25 75 v cc2 = 3.3v v cc2 = 5v i ds = 4ma c bus (pf) 0 t pdf (ns) 250 50 100 150 200 0 500 4312 g05 1500 1000 v cc = v cc2 = v dd, bus = 5v r bus = 2.7k v cc (v) 2 i cc (ma) 8.0 7.5 7.0 6.5 3 4312 g01 6 45 v sdain, sclin = 0v v cc (v) 2 i cc (ma) 3.0 2.5 1.5 2.0 1.0 3 4312 g02 6 45 v sdain, sclin = 0v temperature (c) C50 i ol (ma) 10 5 6 7 8 9 4 50 0 4312 g04 125 25 C25 75 100 v sdain,sclin = 0.4v v sdaout, sclout = 0.4v v cc = v cc2 = 3.3v i bus (ma) 0 v os (mv) 350 100 50 150 200 300 250 0 2 4312 g06 6 4 200mv 100mv driven v sdain, sclin = 50mv v cc = v cc2 = v dd, bus = 5v i bus (ma) 0 v os (mv) 350 100 50 150 200 300 250 0 2 4312 g07 6 4 100mv 200mv driven v sdaout, sclout = 50mv v cc = v cc2 = v dd, bus = 5v t rise(30%C70%) vs c bus c bus (pf) 0 t rise (ns) 150 125 100 75 25 50 0 400 4312 g09 800 200 600 5v 3.3v v cc = v cc2 = v dd, bus acc = 0v temperature (c) C50 i rta (ma) 16 14 12 10 8 6 0 4312 g08 100 C25 25 50 75 3.3v v cc = v cc2 = v dd, bus v sda,scl t v dd,bus acc = 0v c bus = 400pf r bus = 10k 5v
ltc4312 6 4312f pin functions acc : three-state acceleration and buffer mode selector. this pin controls the turn on voltage of the rise time ac- celerators and their current strength on both the input and output sides. it also controls the turn-off voltage of the buffers. see table 1 in the applications information section. discen: disconnect stuck bus enable input. when this pin is high, stuck busses are automatically disconnected and fault is pulled low after a timeout period of 45ms. up to sixteen clock pulses are subsequently applied to the stuck output channels. when discen pin is low, stuck busses are neither disconnected nor clocked but fault is pulled low. connect to gnd if unused. enable1-enable2: connection enable inputs. these input pins enable or disable the corresponding output channel. driving an enable pin low isolates sdain and sclin from the corresponding sdaout and sclout. only enable and disable a channel when all busses are idle. during a bus stuck low fault condition, a falling edge on all enable pins followed by a rising edge on one or more enable pins forces a connection from sdain to the selected sdaout and sclin to the selected sclout. connect to gnd if unused. exposed pad (dfn package only): exposed pad may be left open or connected to device ground. fault : stuck bus fault output. this open drain n-channel mosfet output pulls low if a simultaneous high on the enabled sclout and sdaout channels does not occur in 45ms. in normal operation fault is high. connect a pull up resistor, typically 10k, from this pin to the bus pull-up supply. leave open or tie to gnd if unused. gnd: device ground. sclin: upstream serial bus clock input/output. connect this pin to the scl line on the upstream bus. connect an external pull-up resistor or current source between this pin and the bus supply. do not leave open. sclout1-sclout2: downstream serial bus clock input/ output channels 1-2. connect pins sclout1-sclout2 to the scl lines on the downstream channels 1-2, respec- tively. when in use, an external pull-up resistor or current source is required between the pin and the corresponding bus supply. leave open or tie to gnd and connect the corresponding enable pin to gnd, if unused. sdain: upstream serial bus data input/output. connect this pin to the sda line on the upstream bus. connect an external pull-up resistor or current source between this pin and the bus supply. do not leave open. sdaout1-sdaout2: downstream serial bus data input/ output channels 1-2. connect pins sdaout1-sdaout2 to the sda lines on downstream channels 1-2, respectively. when in use, an external pull-up resistor or current source is required between the pin and the corresponding bus supply. leave open or tie to gnd and connect the cor- responding enable pin to gnd, if unused. v cc : power supply voltage. power this pin from a sup- ply between 2.9v and 5.5v. bypass with at least 0.01f to gnd. v cc2 : output side rise time accelerator (rta) power supply voltage. when powering v cc2 , use a supply volt- age ranging from 2.25v to 5.5v and bypass with at least 0.01f to gnd. if the downstream busses are powered from multiple supply voltages, power v cc2 from the low- est supply voltage. output side rtas are active if v cc2 2.25v and acc is low or open. grounding v cc2 disables output side rtas.
ltc4312 7 4312f block diagram i boost_scl /i boost_sda 4314 bd v il v cc i rta uvlo 110s timer 45ms timer logic sclin sdain discen gnd v cc enable1 enable2 acc v cc i rta vcc2 sclout1 sdaout1 sdaout2 fault sclout2 + C v il v il + C cin din co1 co2 do1 do2 v cc2 i rta v cc2 i rta v cc2 i rta v cc2 i rta en1 en2 mux + C v il + C connect slew rate detector 0.2v/s slew rate detector 0.2v/s slew rate detector 0.2v/s slew rate detector 0.2v/s
ltc4312 8 4312f operation the block diagram shows the major functional blocks of the ltc4312. the ltc4312 is a 1:2 multiplexer with capacitance buffering for i 2 c signals. capacitance buffering is achieved by use of back to back buffers on the clock and data chan- nels which isolate the sdain and sclin capacitances from the sdaout and sclout capacitances respectively. all sda and scl pins are fully bidirectional. the high noise margin allows the ltc4312 to operate with i 2 c devices that drive a non-compliant high v ol . multiplexing is done using n-channel mosfets that are controlled by dedicated enable pins. when enabled, rise time accelerator pull-up currents i rta turn on during rising edges to reduce sys- tem rise time. in a typical application the input side bus is pulled up to v cc and the output side busses are pulled up to v cc2 although these are not requirements. v cc is the primary power supply to the ltc4312. v cc and v cc2 serve as the input and output side rise time accelerator supplies respectively. grounding v cc2 disables the output side accelerators. the multiplexer n-channel mosfet gates of the enabled channels are driven to v cc2 if v cc2 is > 1.8v, otherwise they are driven to v cc . when the ltc4312 ? rst receives power on its v cc pin, it starts out in an undervoltage lockout mode (uvlo) until 110s after v cc exceeds 2.3v. during this time, the buffers and rise time accelerators are disabled, the multiplexer gates are off and the ltc4312 ignores transitions on the clock and data pins independent of the state of the enable pins. v cc2 transitions from a high to a low or vice-versa across a 1.8v threshold also cause the ltc4312 to dis- able the buffers, rise time accelerators and transmission gates and to ignore the clock and data pins until 110s after that transition. assuming that the ltc4312 is not in uvlo mode, when one or both enables are asserted, the ltc4312 activates the connection circuitry between the sdain/sclin inputs and selected output channels. the input rise time accelerators and the output rise time accelerators of the selected channels are also enabled at this time. when a sda/scl input pin or output pin on an enabled output channel is driven below the v il,falling level of 0.33 ? v min , the buffers are turned on and the logic low level is propagated though the ltc4312 to the other side. for v cc2 > 1.8v, v min is the lower of the v cc and v cc2 voltages. for v cc2 < 1.8v, v min is the v cc voltage. the ltc4312 is designed to sink a minimum total bus current i ol of 4ma while holding a v ol of 0.4v. if multiple output channels are enabled, the bus current of all enabled channels needs to be summed to get the total bus current. see the typical performance characteristics curves for i ol as a function of temperature. a high occurs when all devices on the input and output sides release high. once the bus voltages rise above the v il, rising level, which is determined by the state of the acc pin, the buffers are turned off. the rise time accelerators are turned on at a slightly higher voltage. the rise time accelerators accelerate the rising edges of the sda/scl inputs and selected outputs up to voltages of 0.9 ? v cc and 0.8? v cc2 respectively, provided that the busses on their own are rising at a minimum rate of 0.2v/s as determined by the slew rate detectors. acc is a 3-state input that con- trols v il,rising , the rise time accelerator turn-on voltage and the rise time accelerator pull-up strength. the ltc4312 detects a bus stuck low (fault) condition when both clock and data busses are not simultaneously high at least once in 45ms. the voltage monitoring for a stuck low condition is done on the common internal node of the clock and data outputs. hence a stuck low condition is detected only if it occurs on an enabled output channel. when a stuck bus occurs, the ltc4312 asserts the fault ? ag. if discen is tied high, the ltc4312 also disconnects the input and output sides. after waiting at least 40s, it generates up to sixteen 5.5khz clock pulses on the enabled sclout pins and a stop bit to attempt to free the stuck bus. if the bus recovers high before 16 clocks are issued, the ltc4312 ceases issuing clocks and generates a stop bit. if discen is tied low, a stuck bus event only causes fault ? ag assertion. disconnection of the input and output sides and clock generation do not occur. once the stuck bus recovers and the fault has been cleared, in order for a connection to be established between the input and output sides, both enable pins need to be driven low followed by the assertion high of the desired enable pins. when powering into a stuck low condition, the ltc4312 upon exiting uvlo will connect the input and output sides for 45ms until a stuck bus timeout event is detected.
ltc4312 9 4312f applications information the ltc4312 is a 1:2 pin selectable i 2 c multiplexer that provides a high noise margin, capacitance buffering and level translation capability on its clock and data pins. rise time accelerators accelerate rising edges to enable opera- tion at high frequencies with heavy loads. these features are illustrated in the following subsections. rise time accelerators and dc hold-off voltage once the ltc4312 has exited uvlo and a connection has been established between the sda and scl inputs and outputs, the rise time accelerators on both the input and output sides of the sda and scl busses are activated based on the state of the acc pin and the v cc2 supply voltage. during positive bus transitions of at least 0.2v/ s, the rise time accelerators provide pull-up currents to reduce rise time. enabling the rise time accelerators al- lows users to choose larger bus pull-up resistors, reduc- ing power consumption and improving logic low noise margins, to design with bus capacitances outside of the i 2 c speci? cation or to switch at a higher clock frequency. the acc pin sets the turn-off threshold voltage for the buffers, the turn-on voltage for the rise time accelerators, and the rise time accelerator pull-up current strength. the acc functionality is shown in table 1. set acc open or high when a high noise margin is required such as when the ltc4312 is used in a system having i 2 c devices with v ol > 0.4v. table 1. acc control of the rise time accelerator current i rta and buffer turn-off voltage v il,rising acc i rta v rta(th) v il,rising low strong 0.8v 0.6v open 3ma 0.4 ? v min 0.33 ? v min high none n/a 0.33 ? v min the acc pin has a resistive divider between v cc and gnd to set its voltage to 0.5 ? v cc if left open. in the current source accelerator mode, the ltc4312 provides a 3ma constant current source pull-up. in the strong mode, the ltc4312 sources pull-up current to make the bus rise at 75v/s (typical). the strong mode current is therefore directly proportional to the bus capacitance. the ltc4312 is capable of sourcing up to 45ma of current in the strong mode. the effect of the rise time accelerator strength is shown in the sda waveforms in figures 1 and 2 for iden- tical bus loads for a single enabled output channel. the rise time accelerator supplies 3ma and 10ma of pull-up current (i rta ) respectively in the current source and strong modes for the bus conditions shown in figures 1 and 2. the rise time accelerator turn-on voltage in the strong mode is also lower as compared to the current source mode. for identical bus loading conditions, the bus returns high faster in figure 1 compared to figure 2 because of both the higher i rta and the lower turn-on voltage of the rise time accelerator. in each ? gure, note that the input and output rising waveforms are nearly coincident due to the input and output busses having nearly identical bus current and capacitance. figure 1. bus rising edge for the strong accelerator mode figure 2. bus rising edge for the current source accelerator mode 500ns/div 2v/div 4312 f01 0v 0v c in = c out = 200pf r bus = 10k acc = 0 v cc = v cc = 5v sdaout1 sdain 500ns/div 2v/div 4312 f02 0v 0v c in = c out = 200pf r bus = 10k acc = open v cc = v cc2 = 5v sdaout1 sdain
ltc4312 10 4312f applications information figure 3. connection of the ltc4312 in a level shift application. v cc2 is less than or equal to the minimum bus supply voltage on the output side if v cc2 is tied low, the output side rise time accelerators are disabled independent of the state of the acc pin. acc tied high disables input and output rtas. using a combination of the acc pin and the v cc2 voltage allows the user independent control of the input and output side rise time accelerators. the rise time accelerators are also internally disabled during power-up and v cc2 transitions, as described in the operation section, as well as during automatic clocking and stop bit generation for a bus stuck low recovery event. the rise time accelerators when activated pull the bus up to 0.9 ? v cc on the input side of the sda and scl lines. on the output side the sdaout and sclout lines are pulled up by the rise time accelerators to 0.8? v cc2 . for v cc2 voltages approaching 2.3v, acceleration of the output bus may not be seen all the way to 0.8? v cc2 due to the threshold voltage of the nfet pass device. supply voltage considerations in level translation applications care must be taken to ensure that the bus supply voltages on the input and output sides are greater than 0.9 ? v cc and 0.8? v cc2 , respectively, to ensure that the bus is not driven above the bus supplies by the rise time accelerators. this is usually accomplished in a level shifting application by tying v cc to the input bus supply and v cc2 to the minimum bus supply on the output side as shown in figure 3. if v cc2 is grounded, the multiplexer pass gates are powered from v cc . in this case the minimum output bus supply of the enabled channels should be greater than or equal to v cc to prevent cross-conduction between the enabled output channels. this is shown in figure 4. grounding v cc2 as shown in figure 4 disables the output side rise time accelerators independent of the state of the acc pin. the input rise time accelerators in this con? guration continue to be controlled by the acc pin and can be enabled inde- pendently. in figure 4, acc is left open to obtain a high v il and a 3ma rise time accelerator current on the input side. ltc4312 gnd v cc v cc2 4312 f03 sclout1 sdaout1 sclout2 sdaout2 sclout1 sdaout1 sclout2 sdaout2 sclin sdain enable1 enable2 acc discen fault sclin sdain enable1 enable2 3.3v fault r3 10k r2 10k r1 10k c1 0.01f 3.3v 3.3v r5 10k r4 10k c2 0.01f 5v r7 10k r6 10k
ltc4312 11 4312f applications information pull-up resistor value selection to guarantee that the rise time accelerators are activated during a rising edge, the bus must rise on its own with a positive slew rate of at least 0.4v/s. to achieve this, choose a maximum r bus using equation 1: r bus ( ) v dd,bus(min) ? v rta(th) () 0.4 v s ?c bus (1) r bus is the bus pull-up resistor, v dd, bus(min) the minimum bus pull-up supply voltage, v rta(th) the voltage at which the rise time accelerator turns on, which is a function of acc , and c bus the equivalent bus capacitance. r bus values on each output channel must also be chosen to ensure that when all the required output channels are enabled, the total bus current is 4ma. the bus current in each output channel can be 4ma if only one output channel is enabled at any given time. the r bus value on the input side must also be chosen to limit the bus current to be 4ma. the bus current for a single bus is determined by equation 2: i bus (a) = v dd,bus ? 0.4v r bus (2) input to output offset voltage and propagation delay the ltc4312 introduces both an offset as well as a propagation delay for falling edges between the input and output. when a logic low voltage of 200mv is driven on any of the ltc4312s data or clock pins, the ltc4312 regulates the voltage on the opposite side to a slightly higher value. when sclin or sdain is driven to a logic low voltage, sclout or sdaout is driven to a slightly higher voltage as directed by equation 3 which uses sda as an example: v sdaout (v) = v sdain + 45mv + (10 + r mux )? v dd,bus r bus (3) v dd,bus is the output bus voltage, r bus the output bus pull-up resistance and r mux is the resistance of the channel transmission gate in the multiplexer shown in the block diagram. the offset is affected by the v cc2 voltage and bus current. a higher v cc2 voltage (v cc if v cc2 is grounded) reduces r mux leading to a lower offset. see the typical performance characteristics plots for the variation of r mux as a function of v cc2 and temperature. when sdaout or sclout is driven to a logic low voltage 200mv, sclin figure 4. connection of the ltc4312 in a level shift application. v cc is less than or equal to the minimum bus supply voltages on the output side. v cc2 is grounded to disable output rise time accelerators ltc4312 gnd v cc v cc2 4312 f04 sclout1 sdaout1 sclout2 sdaout2 sclout1 sdaout1 sclout2 sdaout2 sclin sdain enable1 enable2 acc discen fault sclin sdain enable1 enable2 3.3v fault r3 10k r2 10k r1 10k c1 0.01f c2 0.01f 3.3v 3.3v r5 10k r4 10k 5v r7 10k r6 10k
ltc4312 12 4312f figure 5. cascading ltc4312s with other ltc4312s and ltc bus buffers. only the sda path is shown for simplicity or sdain is regulated to a logic low voltage as directed by equation 4 which uses sda as an example: v sdain (v) = v sdaout + 45mv + 10 ? v dd,bus r bus (4) the sclout/sdaout to sclin/sdain offset is lower than the reverse case as the multiplexer transmission gate does not affect this offset. for driven logic low voltages < 200mv, the above equations do not apply as the saturation voltage of the open collector output transistor results in a higher offset. however, the offset is guaranteed to be less than 400mv for a total bus pull-up current of 4ma under all conditions. see the typical performance characteristics curves for the buffer offset voltage as a function of the driven logic low voltage and bus pull-up current. the high-to-low propagation delay arises due to both the ? nite response time of the buffers and their ? nite current sink capability. see the typical performance characteristics curves for the propagation delay as a function of the bus capacitance. applications information cascading ltc4312 devices and other ltc bus buffers multiple ltc4312s can be cascaded or the ltc4312 may be cascaded with other ltc bus buffers as required by the application. this is shown for the data pathway in figure 5 where an ltc4312 is cascaded with other ltc4312s and some select ltc bus buffers. the clock path is identical. when using such cascades, users should be aware of the additive logic low offset voltages (v os ) when determin- ing system noise margin. if the sum of the offsets (refer to equations 3 and 4 and to the data sheets of the cor- responding bus buffers) plus the worst-case driven logic low voltage across the cascade exceeds the buffer turn off voltage, signals will not be propagated across the cascade. also the minimum rise time accelerator (rta) turn-on volt- age (wherever applicable) of each device in the cascade should also be greater than the maximum buffer turn-off voltage of all the devices in the cascade. this condition is required to prevent contention between one devices buffer and anothers rta. based on this requirement, ltc4312 gnd 3.3v r1 10k c1 0.01f v cc v cc2 4312 f05 sdaout1 sdaout2 sdain acc 3.3v ltc4312 v cc v cc2 sdaout1 sdaout2 sdain acc ltc4301 gnd v cc sdaout sdain 5v ltc4312 gnd 3.3v c2 0.01f v cc v cc2 sdaout1 sdaout2 sdain acc c3 0.01f r2 10k r3 10k r4 10k c4 0.01f c5 0.01f r5 10k r6 10k 5v 3.3v r7 10k sdaout1 sdaout2 sdaout3 sdaout4 sdaout5 ltc4303 v cc sdaout sdain 5v r8 10k ltc4307 v cc sdaout sdain 5v r9 10k gnd gnd gnd
ltc4312 13 4312f applications information the ltc4312 can be cascaded with the ltc4303 and ltc4307 if the ltc4312s rta turn-on voltage is set to be 0.8v ( acc low). the ltc4312 can be cascaded with the ltc4301 and ltc4301l under all acc settings as these devices do not have rtas. the ltc4312 can be cascaded with the ltc4302, ltc4304, ltc4305 and ltc4306 if the ltc4312s rtas are set to turn on at 0.8v ( acc low) or under all acc settings if the rtas on the other bus buf- fers are disabled. finally, two ltc4312s can be cascaded if their acc pins are tied to the same state, high, low or open or if the acc pin of one ltc4312 is tied high and the other is left open. radial telecommunications figure 6 shows the use of the ltc4312 in a radial telecom- munications application. two shelf managers are wired to communicate with slave i 2 c devices for redundancy. each shelf manager can have as many ltc4312s as required depending on the number of boards in the system and the desired radial/star con? guration. the enable pins of the ltc4312s inside only one shelf manager are asserted high at any time. for simplicity, in figure 6 only the sda pathway is shown. the scl pathway is identical. figure 6. ltc4312s con? gured for a radially connected redundant telecommunications shelf manager application in a 12 2 arrangement. the enable pins on only one of the shelf managers are high at any time. only the sda path is shown for simplicity ltc4312 #1 gnd v cc 3.3v v cc2 shmc #1 shmc #2 (identical to shmc#1) 4312 f06 sdaout1 sdaout2 sdain enable1 enable2 acc enable1a enable2a p r1 10k backplane ipmb-a sda1 ipmb-a sda24 ipmb-b sda1 sda24 sda1 fru #1 fru #24 3.3v r2 10k 3.3v t tt t tt t tt ltc4312 #12 gnd v cc 3.3v v cc2 sdaout1 sdaout2 sdain enable1 enable2 acc enable23a enable24a r3 10k 3.3v t tt ipmb-a (24) ipmb-b (24) ipmb-b (24) ipmb-b sda24 t tt sda24 sda1 t tt
ltc4312 14 4312f applications information nested addressing the ltc4312 can provide nested addressing when its enable pins are used as channel select bits. this is shown in figure 7 where the master communicates with slave devices that have the same address by selectively enabling only one output channel at a time. since slaves have the same address care must be taken that the master never enables both channels at the same time. stop bit generation and fault clocking if the output bus sticks low (sclout or sdaout stuck low for at least 45ms) on one of the enabled channels and discen is high, the ltc4312 attempts to unstick the bus by ? rst breaking the connection between the input and output, asserting fault low and generating up to 16 clock pulses at 5.5khz on the sclout node common to the two channels. should the stuck bus release high during this period, clock pulsing is stopped, a stop bit is generated and fault is cleared. in order for a connec- tion to be established between the input and output, all enables have to be taken low followed by an assertion of the enables of the required channels.this process is illustrated in figure 8 for the case where only channel 1 is active and sdaout1 starts out stuck low and then recov- ers. if discen is tied low and a stuck low event occurs, the fault ? ag is driven low, but the connection between the input and output is not broken and clock generation is not done. ltc4312 gnd v cc v cc2 4312 f07 sclout1 sdaout1 sclout2 sdaout2 sclin sdain enable1 enable2 acc discen fault enable1 enable2 3.3v r3 10k fault r2 10k r1 10k c1 0.01f c2 0.01f 3.3v 3.3v r5 10k r4 10k address = 1001 000 address = 1001 000 5v r7 10k r6 10k i 2 c device i 2 c device i 2 c device figure 7. nested addressing figure 8.bus waveforms during a sdaout stuck low and recovery event 1ms/div 4312 f08 connect at rising edge of enable1 disconnect at timeout stuck low > 45ms automatic clocking driven low recovers sclout1 5v/div sdaout1 5v/div sdain 5v/div enable1 5v/div
ltc4312 15 4312f applications information applications information demultiplexer function due to its bi-directional nature, the ltc4312 can be used as a demultiplexer. this is shown in figure 9 where two channels are used to drive i 2 c data from the master side with redundancy to the slave side. in this application the sdaout/sclout channels serve as the inputs while the sdain/sclin channel is the output. redundancy on the master side provides protection against power supply failure. in figure 9, if the 5v bus supply on channel 1 falls below 1.4v, channel 1 gets disabled as enable1 is driven below its digital threshold. simultaneously, the v be of the npn pull-down device on enable2 falls below 0.7v and it turns off. this causes enable2 to be pulled up by r7 which in turn enables channel 2, causing control to be transferred to the backup i 2 c master device. figure 9. the ltc4312 con? gured as a 2:1 demultiplexer in a system with redundancy ltc4312 gnd v cc2 v cc 4312 f09 sdain sclin acc discen fault sdaout1 sclout1 enable1 sdaout2 sclout2 enable2 c1 0.01f sda scl fault 3.3v r9 10k r8 10k r1 10k r2 10k 5v r3 10k r4 10k r5 100k 3.3v r10 10k r7 20k r6 50k primary i 2 c master controller card backup i 2 c master controller card bf840
ltc4312 16 4312f applications information ltc4312 gnd v cc v cc2 4312 f10 sclout1 sdaout1 sclout2 sdaout2 sclin sdain enable1 enable2 acc discen fault enable1 enable2 3.3v fault r3 10k r2 10k r1 10k c1 0.01f c2 0.01f 3.3v 3.3v r5 10k r4 10k 5v r7 10k r6 10k i 2 c device v ol = 0.6v i 2 c device io card connector i 2 c device io card connector figure 10. sda, scl hot swap? and operation with a non-compliant i 2 c device hot-swapping figure 10 shows the ltc4312 in a typical hot-swapping application where the ltc4312 is on the backplane and i/o cards plug into the downstream channels. the outputs must idle high and the corresponding output channel must be disabled before an i/0 card can be plugged or unplugged from an output channel. figure 10 also shows the use of a non-compliant i 2 c device with the ltc4312. the high noise margin of the ltc4312 supports logic low levels up to 0.3 ? v cc , allowing devices to drive greater than 0.4v logic low levels on the clock and data lines.
ltc4312 17 4312f applications information level translating to bus voltages < 2.25v the ltc4312 can be used for level translation to bus volt- ages below 2.25v if certain conditions are met. in order to perform this level translation, rtas on the low voltage side need to be disabled in order to prevent an over drive of the low voltage bus. if one of the output channels is pulled up to the low voltage bus supply, the other output channel needs to be disabled when this channel is active, in order to prevent cross conduction between the output channels. since the buffer turn-on and turn-off voltages are 0.3? v min , the minimum bus supply voltage is deter- mined by equation 5: v dd,bus(min) 0.3 ? v min 0.7 (5) in order to meet the v ih = 0.7 ? v dd,bus requirement and not impact the high side noise margin. users willing to live with a lower logic high noise margin can level translate down to 1.5v. an example of voltage level translation from 3.3v to 1.8v is illustrated in figure 11, where a 3.3v input voltage level is translated to a 1.8v output voltage level on channel 1. tying v cc to 3.3v satis? es equation 5. ground- ing v cc2 disables the rta on the low voltage channel. v min defaults to v cc under these conditions, making the buffer turn off voltage 0.99v. channel 2 must be disabled when channel 1 is enabled. a similar voltage translation can also be performed going from a 3.3v bus supply on the output side to a 1.8v bus supply on the input side if acc is tied high to disable the input rta and if v cc and v cc2 are tied to the output side bus supply. figure 11. level shifting down to 1.8v using the ltc4312, v cc2 is grounded to disable the rise time accelerator on the low voltage bus. enable2 must be low whenever enable1 is high ltc4312 gnd v cc v cc2 4312 f11 sclout1 sdaout1 sclout2 sdaout2 sclout1 sdaout1 sclout2 sdaout2 sclin sdain enable1 enable2 acc discen fault 3.3v r2 10k r1 10k sclin sdain enable1 enable2 c1 0.01f 3.3v 1.8v r5 10k r4 10k c2 0.01f c3 0.01f 5v r7 10k r6 10k r3 10k
ltc4312 18 4312f package description de package 14-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1708 rev b) 3.00 0.10 (2 sides) 4.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wged-3) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 3.00 ref 1.70 0.05 1 7 14 8 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (de14) dfn 0806 rev b pin 1 notch r = 0.20 or 0.35 45 chamfer 3.00 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 package outline 0.25 0.05 0.25 0.05 0.50 bsc 3.30 0.05 3.30 0.10 0.50 bsc
ltc4312 19 4312f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description ms package 16-lead plastic msop (reference ltc dwg # 05-08-1669 rev ?) msop (ms16) 1107 rev ? 0.53 p 0.152 (.021 p .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 C?0.27 (.007 C .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16151413121110 12345678 9 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 o C 6 o typ detail a detail a gauge plane 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 p 0.127 (.035 p .005) recommended solder pad layout 0.305 p 0.038 (.0120 p .0015) typ 0.50 (.0197) bsc 4.039 p 0.102 (.159 p .004) (note 3) 0.1016 p 0.0508 (.004 p .002) 3.00 p 0.102 (.118 p .004) (note 4) 0.280 p 0.076 (.011 p .003) ref 4.90 p 0.152 (.193 p .006)
ltc4312 20 4312f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 1210 ? printed in usa related parts typical application part number description comments ltc4300a-1/ ltc4300a-2/ ltc4300a-3 hot-swappable 2-wire bus buffers -1: bus buffer with ready and enable -2: dual supply buffer with acc -3: dual supply buffer with enable ltc4302-1/ ltc4302-2 addressable 2-wire bus buffer address expansion, gpio, software controlled ltc4303 ltc4304 hot-swappable 2-wire bus buffer with stuck bus recovery provides automatic clocking to free stuck i 2 c busses ltc4305 ltc4306 2- or 4-channel, 2-wire bus multiplexers with capacitance buffering 2 or 4 software selectable downstream busses, stuck bus disconnect, rise time accelerators, fault reporting, 10kv hbm esd tolerance ltc4307 low offset hot-swappable 2-wire bus buffer with stuck bus recovery 60mv bus offset, 30ms stuck bus disconnect and recovery, rise time accelerators, 5kv hbm esd tolerance ltc4307-1 high de? nition multimedia interface (hdmi) level shifting 2-wire bus buffer 60mv buffer offset, 3.3v to 5v level shifting, 5kv hbm esd tolerance ltc4308 low voltage, level shifting hot-swappable 2-wire bus buffer with stuck bus recovery bus buffer with enable and ready, level translation to 1v busses, output side rise time accelerators ltc4309 low offset hot-swappable 2-wire bus buffer with stuck bus recovery 60mv buffer offset, 30ms stuck bus disconnect and recovery, rise time accelerators, 5kv hbm esd tolerance ltc4310-1/ ltc4310-2 hot-swappable i 2 c isolators -1: 100khz bus -2: 400khz bus ltc4311 low voltage i 2 c/smbus accelerator rise time acceleration with enable and 8kv hbm esd tolerance ltc4314 pin-selectable, 4-channel, 2-wire multiplexer with bus buffer 4 pin-selectable downstream busses, stuck bus disconnect and recovery, selectable rise time accelerator current and activation voltage, 4kv hbm esd tolerance ltc4301 supply independent hot swappable 2-wire bus buffer bus buffer with 1v pre-charge, cs and ready ltc4301l hot-swappable 2-wire bus buffer with low voltage level translation bus buffer with cs and ready allowing for input bus voltages of up to 1v ltc1694-1 smbus/i 2 c accelerator rise time accelerator level translating 2.5v, 3.3v and 5v busses and operation with a non-compliant i 2 c device ltc4312 gnd v cc v cc2 4312 ta02 sclout1 sdaout1 sclout2 sdaout2 sclout1 sdaout1 sclout2 sdaout2 sclin sdain enable1 enable2 acc discen 3.3v r2 10k r1 10k c1 0.01f 3.3v 5v r4 10k r3 10k c2 0.01f 2.5v r6 10k r5 10k non-compliant i 2 c device v ol = 0.6v

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